Consider a system with the following specifications:

Physical Address = 4 bits, Logical Address = 3 bits, Page Size = 4 bytes

1. Click on PROCESS to generate a process of size 8B, consisting of 8 instructions, each 1B in size.
   • Observe that the process will be divided into two pages, P0 and P1, each 4 bytes in size. Then, the process will be loaded into secondary memory.
2. Click on LOAD to load the process from secondary memory into main memory.
3. Click on TABLE to generate a page table and store the base address of the page table in the Page Table Base Register (PTBR).
4. Click on the CPU image to generate the logical address.
5. Click on the PLUS sign to initiate scaling.

   Page Table Entry = PTBR + Page Number * Page Size

   • Enter the PTBR value.
   • Enter the value for the Page Number (p) given in the logical address.
   • Click on the SUBMIT button to get the actual location of the page entry in the table.
6. Observe how the mapping is performed.

NOTE: To get a clear view of a page or frame in memory, move your cursor over that particular cell.