To Implement Paging Technique for Memory Management

Post Test

1. A process has a virtual address space of 16KB and the page size is 2KB. How many pages are required for this process?

a) 4
b) 8
c) 16
d) 32

2. A system has a 16-bit logical address and a page size of 512 bytes. How many pages are available in the logical address space?

a) 32
b) 64
c) 128
d) 256

3. Consider a system where the Page Table Base Register is set to 2000. The page size is 100 bytes, and the page number is 5. What will be the Page Table Entry?

a) 2050
b) 2100
c) 2500
d) 2600

4. A process has a virtual address space of 64 KB, and the page size is 4 KB. If the physical memory has 16 KB, how many page frames are available for the process?

a) 4
b) 8
c) 16
d) 64

5. A system with 16-bit logical addresses and a 4 KB page size has how many bits dedicated to the page offset within a logical address?

a) 4
b) 8
c) 12
d) 16